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november 2008 rev 5 1/20 20 ne555 sa555 - se555 general-purpose single bipolar timers features low turn-off time maximum operating frequency greater than 500 khz timing from microseconds to hours operates in both astable and monostable modes output can source or sink up to 200 ma adjustable duty cycle ttl compatible temperature stability of 0.005% per c description the ne555 monolithic timing circuit is a highly stable controller capable of producing accurate time delays or oscillation. in the time delay mode of operation, the time is precisely controlled by one external resistor and capacitor. for a stable operation as an oscilla tor, the free running frequency and the duty cycle are both accurately controlled with two external resistors and one capacitor. the circuit may be triggered and reset on falling waveforms, and the output structure can source or sink up to 200 ma. n dip8 (plastic package) d so8 (plastic micropackage) 1 2 3 45 6 7 8 1 - gnd 2 - trigger 3 - output 4 - reset 5 - control voltage 6 - threshold 7 - discharge 8 - v cc pin connections (top view) www.st.com
schematic diagrams ne555 - sa555 - se555 2/20 1 schematic diagrams figure 1. block diagram figure 2. schematic diagram threshold comp 5k 5k 5k trigger r flip-flop s q discharge out inhibit/ reset reset comp s - 8086 s + control voltage v cc

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ne555 - sa555 - se555 absolute maxi mum ratings and operating conditions 3/20 2 absolute maximum ratings and operating conditions table 1. absolute maximum ratings symbol parameter value unit v cc supply voltage 18 v i out output current (sink & source) 225 ma r thja thermal resistance junction to ambient (1) dip8 so-8 1. short-circuits can c ause excessive heating. t hese values are typical. 85 125 c/w r thjc thermal resistance junction to case (1) dip8 so-8 41 40 c/w esd human body model (hbm) (2) 2. human body model: a 100 pf capacit or is charged to the specified voltage, then discharged through a 1.5k resistor between two pins of the device. this is done for all couples of connected pin combinations while the other pins are floating. 1000 v machine model (mm) (3) 3. machine model: a 200 pf capacitor is charged to the specified voltage, then discharged directly between two pins of the device with no external series resistor (internal resistor < 5 ). this is done for all couples of connected pin combinations whil e the other pins are floating. 100 charged device model (cdm) (4) 4. charged device model: all pins and the package are charged together to the specified voltage and then discharged directly to the ground through only one pin. th is is done for all pins. 1500 latch-up immunity 200 ma t lead lead temperature (soldering 10 seconds) 260 c t j junction temperature 150 c t stg storage temperature range -65 to 150 c table 2. operating conditions symbol parameter value unit v cc supply voltage ne555 sa555 se555 4.5 to 16 4.5 to 16 4.5 to 18 v v th , v trig , v cl , v reset maximum input voltage v cc v i out output current (sink and source) 200 ma t oper operating free air temperature range ne555 sa555 se555 0 to 70 -40 to 105 -55 to 125 c
electrical characteristics ne555 - sa555 - se555 4/20 3 electrical characteristics table 3. t amb = +25 c, v cc = +5 v to +15 v (unless otherwise specified) symbol parameter se555 ne555 - sa555 unit min. typ. max. min. typ. max. i cc supply current (r l = ) low state v cc = +5v v cc = +15v high state v cc = +5v 3 10 2 5 12 3 10 2 6 15 ma timing error (monostable) (r a = 2k to 100k , c = 0.1 f) initial accuracy (1) drift with temperature drift with supply voltage 0.5 30 0.05 2 100 0.2 1 50 0.1 3 0.5 % ppm/c %/v timing error (astable) (r a , r b = 1k to 100k , c = 0.1 f, v cc = +15v) initial accuracy (1) drift with temperature drift with supply voltage 1.5 90 0.15 2.25 150 0.3 % ppm/c %/v v cl control voltage level v cc = +15v v cc = +5v 9.6 2.9 10 3.33 10.4 3.8 9 2.6 10 3.33 11 4 v v th threshold voltage v cc = +15v v cc = +5v 9.4 2.7 10 3.33 10.6 4 8.8 2.4 10 3.33 11.2 4.2 v i th threshold current (2) 0.1 0.25 0.1 0.25 a v trig trigger voltage v cc = +15v v cc = +5v 4.8 1.45 5 1.67 5.2 1.9 4.5 1.1 5 1.67 5.6 2.2 v i trig trigger current (v trig = 0v) 0.5 0.9 0.5 2.0 a v reset reset voltage (3) 0.4 0.7 1 0.4 0.7 1 v i reset reset current v reset = +0.4v v reset = 0v 0.1 0.4 0.4 1 0.1 0.4 0.4 1.5 ma v ol low level output voltage v cc = +15v i o(sink) = 10ma i o(sink) = 50ma i o(sink) = 100ma i o(sink) = 200ma v cc = +5v i o(sink) = 8ma i o(sink) = 5ma 0.1 0.4 2 2.5 0.1 0.05 0.15 0.5 2.2 0.25 0.2 0.1 0.4 2 2.5 0.3 0.25 0.25 0.75 2.5 0.4 0.35 v v oh high level output voltage v cc = +15v i o(sink) = 200ma i o(sink) = 100ma v cc = +5v i o(sink) = 100ma 13 3 12.5 13.3 3.3 12.75 2.75 12.5 13.3 3.3 v
ne555 - sa555 - se555 electrical characteristics 5/20 i dis(off) discharge pin leakage current (output high) v dis = 10v 20 100 20 100 na v dis(sat) discharge pin saturation voltage (output low) (4) v cc = +15v, i dis = 15ma v cc = +5v, i dis = 4.5ma 180 80 480 200 180 80 480 200 mv t r t f output rise time output fall time 100 100 200 200 100 100 300 300 ns t off turn off time (5) (v reset = v cc )0.50.5s 1. tested at v cc = +5 v and v cc = +15 v. 2. this will determine th e maximum value of r a + r b for 15 v operation. the maximum total (r a + r b ) is 20 m for +15 v operation and 3.5 m for +5 v operation. 3. specified with trigger input high. 4. no protection against excessive pin 7 current is necessary, providing the package dissipation rating is not exceeded. 5. time measured from a positive pulse (from 0 v to 0.8 x v cc ) on the threshold pin to the transition from high to low on the output pin. trigger is tied to threshold. table 3. t amb = +25 c, v cc = +5 v to +15 v (unless otherwise specified) (continued) symbol parameter se555 ne555 - sa555 unit min. typ. max. min. typ. max.
electrical characteristics ne555 - sa555 - se555 6/20 figure 3. minimum pulse width required for triggering figure 4. supply current versus supply voltage figure 5. delay time versus temperature figure 6. low output voltage versus output sink current figure 7. low output voltage versus output sink current figure 8. low output voltage versus output sink current
ne555 - sa555 - se555 electrical characteristics 7/20 figure 9. high output voltage drop versus output figure 10. delay time versus supply voltage figure 11. propagation delay versus voltage level of trigger value
application information ne555 - sa555 - se555 8/20 4 application information 4.1 monostable operation in the monostable mode, the timer generates a single pulse. as shown in figure 12 , the external capacitor is initially held discharged by a transistor inside the timer. figure 12. typical schematics in monostable operation the circuit triggers on a negative-going input signal when the level reaches 1/3 v cc . once triggered, the circuit remains in this state until the set time has elapsed, even if it is triggered again during this interval. the duration of the output high state is given by t = 1.1 r 1 c 1 and is easily determined by figure 14 . note that because the charge rate and the threshold level of the comparator are both directly proportional to supply voltage, the timing interval is independent of supply. applying a negative pulse simultaneously to the reset terminal (pin 4) and the trigger terminal (pin 2) during the timing cycle discharges the external capacitor and causes the cycle to start over. the timing cycle now starts on t he positive edge of the reset pu lse. during the time the reset pulse is applied, the output is driven to its low state. when a negative trigger pulse is applied to pin 2, the flip-flop is set, releasing the short- circuit across the external capacitor and dr iving the output high. the voltage across the capacitor increases exponentially with the time constant t = r 1 c 1 . when the voltage across the capacitor equals 2/3 v cc , the comparator resets the flip-flop which then discharges the capacitor rapidly and drives the output to its low state. figure 13 shows the actual waveforms generated in this mode of operation. when reset is not used, it should be tied high to avoid any possibility of unwanted triggering. reset trigger output r1 c1 control voltage 0.01 f ne555 = 5 to 15v v cc 4 2 3 1 5 6 7 8
ne555 - sa555 - se555 application information 9/20 figure 13. waveforms in monostable operation figure 14. pulse duration versus r1c1 4.2 astable operation when the circuit is connected as shown in figure 15 (pins 2 and 6 connected) it triggers itself and free runs as a multi-vibrator. the external capacitor charges through r 1 and r 2 and discharges through r 2 only. thus the duty cycle can be set accurately by adjusting the ratio of these two resistors. in the astable mode of operation, c 1 charges and discharges between 1/3 v cc and 2/3 v cc . as in the triggered mode, the charge and discharge times and, therefore, frequency are independent of the supply voltage. capacitor voltage = 2.0v/div t = 0.1 ms / div input = 2.0v/div output voltage = 5.0v/div r1 = 9.1k , c1 = 0.01 f, r = 1k l c ( f) 10 1.0 0.1 0.01 0.001 10 100 1.0 10 100 10 (t ) d s s ms ms ms s 10m 1m 1 00 k 10k r1 = 1k
application information ne555 - sa555 - se555 10/20 figure 15. typical schematics in astable operation figure 16 shows the actual waveforms generated in this mode of operation. the charge time (output high) is given by: t1 = 0.693 (r 1 + r 2 ) c 1 and the discharge time (output low) by: t2 = 0.693 (r 2 ) c 1 thus the total period t is given by: t = t1 + t2 = 0.693 (r1 + 2r2) c1 the frequency of o scillation is then: it can easily be found from figure 17 . the duty cycle is given by: output 3 4 8 7 5 1 r1 c1 2 6 r2 control voltage ne555 v cc = 5 to 15v 0.01 f f = 1 t --- 1.44 r1 2r2 + () c1 -------------------------------------- - = d r2 r1 2r2 + ------------------------- - =
ne555 - sa555 - se555 application information 11/20 figure 16. waveforms in astable operation figure 17. free running frequency versus r 1 , r 2 and c 1 t = 0.5 ms / div output voltage = 5.0v/div capacitor voltage = 1.0v/div r1 = r2 = 4.8k , c1= 0.1 f, r = 1k ( f) 10 1.0 0.1 0.01 0.001 0.1 1 10 100 1k 10k f (hz) o 1 m r 1 + r 2 = 1 0 m 1 0 0 k 1 0 k 1 k
application information ne555 - sa555 - se555 12/20 4.3 pulse width modulator when the timer is connected in the monostable mode and triggered with a continuous pulse train, the output pulse width can be modulated by a signal applied to pin 5. figure 18 shows the circuit. figure 18. pulse width modulator 4.4 linear ramp when the pull-up resistor, r a , in the monostable circuit is replaced by a constant current source, a linear ramp is generated. figure 19 shows a circuit configuration that will perform this function. figure 19. linear ramp trigger output r c ne555 2 4 3 1 5 6 7 modulation input 8 a v cc trigger output c ne555 2 4 3 1 5 6 7 8 e v cc 0.01 f r2 r1 r 2n4250 or equiv.
ne555 - sa555 - se555 application information 13/20 figure 20 shows the waveforms generator by the linear ramp. the time interval is given by: figure 20. linear ramp 4.5 50% duty cycle oscillator for a 50% duty cycle, the resistors r a and r b can be connected as in figure 21 . the time period for the output high is the same as for astable operation (see section 4.2 on page 9 ): t1 = 0.693 r a c for the output low it is thus the frequency of oscillation is: t = (2/3 vcc re (r1+r2) c r1 vcc - vbe (r1+r2) --------------------------------------------------------------- - vbe = 0.6v v cc = 5 v time: 20 s/div r 1 + 47 k r 2 = 100 k r e = 2.7 k c = 0.01 f top trace: input 3 v/div middle trace: output 5 v/div bottom trace: output 5 v/div bottom trace: capacitor voltage 1 v/div t 2 [(r. rb)/(ra+rb)].c.ln rb 2ra ? 2rb ra ? -------------------------- - = f 1 t1 t2 + ---------------- - =
application information ne555 - sa555 - se555 14/20 figure 21. 50% duty cycle oscillator note that this circui t will not oscillate if r b is greater than 1/2 r a because the junction of r a and r b cannot bring pin 2 down to 1/3 v cc and trigger the lower comparator. 4.6 additional information adequate power supply bypassing is necess ary to protect associated circuitry. the minimum recommended is 0.1 f in parallel with 1 f electrolytic. out r a c ne55 2 4 3 1 5 6 7 8 v cc 51k r b 22k 0.01 f v cc 0.01 f
ne555 - sa555 - se555 package information 15/20 5 package information in order to meet environmental requirements, stmicroelectronics offers these devices in ecopack ? packages. these packages have a lead-free second level interconnect. the category of second level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. ecopack is an stmicroelectronics trademark. ecopack specifications are available at: www.st.com .
package information ne555 - sa555 - se555 16/20 5.1 dip8 package information figure 22. dip8 package mechanical drawing table 4. dip8 package mechanical data ref. dimensions millimeters inches min. typ. max. min. typ. max. a5.330.210 a1 0.38 0.015 a2 2.92 3.30 4.95 0.115 0.130 0.195 b 0.36 0.46 0.56 0.014 0.018 0.022 b2 1.14 1.52 1.78 0.045 0.060 0.070 c 0.20 0.25 0.36 0.008 0.010 0.014 d 9.02 9.27 10.16 0.355 0.365 0.400 e 7.62 7.87 8.26 0.300 0.310 0.325 e1 6.10 6.35 7.11 0.240 0.250 0.280 e 2.54 0.100 ea 7.62 0.300 eb 10.92 0.430 l 2.92 3.30 3.81 0.115 0.130 0.150
ne555 - sa555 - se555 package information 17/20 5.2 so-8 package information figure 23. so-8 package mechanical drawing table 5. so-8 package mechanical data ref. dimensions millimeters inches min. typ. max. min. typ. max. a1.750.069 a1 0.10 0.25 0.004 0.010 a2 1.25 0.049 b 0.28 0.48 0.011 0.019 c 0.17 0.23 0.007 0.010 d 4.80 4.90 5.00 0.189 0.193 0.197 e 5.80 6.00 6.20 0.228 0.236 0.244 e1 3.80 3.90 4.00 0.150 0.154 0.157 e 1.27 0.050 h 0.25 0.50 0.010 0.020 l 0.40 1.27 0.016 0.050 l1 1.04 0.040 k 0 8 1 8 ccc 0.10 0.004
ordering information ne555 - sa555 - se555 18/20 6 ordering information table 6. order codes part number temperature range package packing marking ne555n 0c, +70c dip8 tube ne555n ne555d/dt so-8 tube or tape & reel ne555 sa555n -40c, +105c dip8 tube sa555n SA555D/dt so-8 tube or tape & reel sa555 se555n -55c, + 125c dip8 tube se555n se555d/dt so-8 tube or tape & reel se555
ne555 - sa555 - se555 revision history 19/20 7 revision history table 7. document revision history date revision changes 01-jun-2003 1 initial release. 2004-2006 2-3 internal revisions 15-mar-2007 4 expanded order code table. template update. 06-nov-2008 5 added i out value in table 1: absolute maximum ratings and table 2: operating conditions . added esd tolerance, latch-up tolerance, r thja and r thjc in table 1: absolute maximum ratings .
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